HyperTransport
HyperTransport is a CPU to I/O and CPU to CPU bus design.
HyperTransport is an open standard which has been incorporated into AMD's Opteron and Athlon64 64-bit x86 processors, Transmeta's Efficeon x86 processor, Broadcom's BCM1250 64-bit MIPS processor, and PMC-Sierra's RM9000 64-bit MIPS processor family.
Integrating HyperTransport into the CPU enables the elimination of the Front Side Bus along with the performance penalties usually associated with that bus.
HyperTransport affects more than the CPU though. HyperTransport is a complete system bus which integrates PCI, PCI-X, USB, FireWire, AGP 8x, InfiniBand, PL-2, SPI, and Gigabit Ethernet.
HyperTransport provides up to 22.4 Gigabyte/second aggregate CPU to I/O or CPU to CPU bandwidth.
HyperTransport Technology
HyperTransport utilizes a packet-based protocol to maximize flexibility while minimizing the number of data paths required for command and control.
HyperTransport is a point-to-point architecture instead of a shared architecture like PCI or PCI-X.
HyperTransport is built upon 1.2 volt Low Voltage Differential Signaling (LVDS) to reduce signal noise.
HyperTransport Competitors
Technologies competing with HyperTransport include:
- PCI
- PCI-X
- SysAD
- RapidIO
- PCI Express
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- Front Side Bus
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