SerDes (pronounced sir-dees) stands for Serializer/Deserializer. It is a set of blocks that is commonly found in high speed communications. SerDes’ general purpose is to compensate for limited input/output. The blocks can convert data between serial data and interfaces that are parallel in different directions.
Functions of SerDes
The generic function is made up of two blocks:
- Parallel In Serial Output (PISO)
- Serial In Parallel Output (SIPO)
Additionally, there are four different SerDes architectures. They are:
- Parallel Clock SerDes
- Embedded Clock SerDes
- 8b/10b SerDes
- Bit interleaved SerDes
Parallel Input Serial Output
PISO usually has a set of data input lines, input data latches, and a parallel clock input. The most basic form of PISO has a single shift register. This register receives the parallel data only once per parallel clock, then shifts it out at the much higher serial clock rate.
Serial In Parallel Output
On the other hand, SIPO has a receive clock output, data output lines, and output data latches. When implemented, there are typically two registers used on SIPO. The first one is used to clock in the serial stream, while the second is used to hold data that is for the slower parallel side. These two registers are connected to act as a double buffer.
Parallel Clock SerDes
This type of SerDes serializes a parallel bus input. It is used along with control signals and a data address. This stream that has been serialized is then sent along with a reference clock. This clock’s jitter tolerance is anywhere from 5-10 ps rms when dealing with the serializer.
Embedded Clock SerDes
This method takes both data and clock and serializes them into a single stream. At first, one cycle of clock signal is transmitted. Once that happens, the data bit stream follows. Because the clock is embedded and can be recovered, the serialized clock jitter tolerance can be relaxed up to 80-120 pps rms.The reference clock disparity at the deserializer can be +/- 50000 ppm.
This type of SerDes makes each data byte comparable to a 10bit code and then serializes the data. The deserializer then uses the reference clock as a way to monitor the clock recovered from the bit stream. As the information is synthesized into the bit stream, the transmitter clock jitter tolerance can be anywhere from 5-10 ps rms. The reference clock disparity is +/- 100ppm.
Bit Interleaved SerDes
This multiplexes slow serial data streams and makes them into fast serial streams. The receiver then demultiplexes these fast bit streams and makes them into slower streams that are easier to work with and interpret.